In a Control Module (CM) that includes a Central Processing Unit (CPU) and a power supply controller and is equipped within a storage device, a power supply voltage of the CPU is controlled based on a VID (Voltage Identification) signal that the CPU provides to the power supply controller. The power supply controller provides the CPU with the power supply voltage according to the VID value provided from the CPU. In providing the VID value from the CPU to the power supply controller, parallel VID signals are transmitted by using an asynchronous parallel VID bus including eight signal lines. In addition, monitoring a VID signal and testing a voltage margin may be performed between the CPU and the power supply controller.
With recent improvements in the performance of CPUs, it is under consideration to use a synchronous serial VID bus allowing a clock signal, a data signal, or an alarm signal to be transmitted and received between a CPU and a power supply controller, instead of the asynchronous parallel VID bus. Data flowing on the conventional asynchronous parallel VID bus is merely a VID signal notification command transmitted from the CPU to the power supply controller. However, in the synchronous serial VID bus, a power supply controller information acquisition command is transmitted from the CPU to the power supply controller in addition to the VID value notification command as described above, while a reception response command is transmitted from the power supply controller to the CPU. As such, a variety of information flows in both directions. In addition, the CPU may need to receive the reception response command from the power supply controller within a specified period of time after a corresponding command is transmitted to the power supply controller.
Related art is disclosed in Japanese Laid-open Patent Publication No. 2001-320390, Japanese Laid-open Patent Publication No. 2009-94550 and Japanese Laid-open Patent Publication No. 2000-316036.
However, although the asynchronous parallel VID bus between the CPU and the power supply controller is simply replaced with the synchronous serial VID bus, such a CM has a problem in that data signals are not transmitted from the power supply controller to the CPU. In addition, since the CPU does not receive data signals from the power supply controller, there is also a problem that the CPU erroneously recognizes the power controller to be in an abnormal state even when the power supply controller is in a normal state.